<html><body><samp><pre>
<!@TC:1399961659>
#Build: Synplify Pro E-2010.09A-1, Build 006R, Oct  6 2010
#install: d:\Microsemi\Libero_v9.1\Synopsys\synplify_E201009A-1
#OS:  6.1
#Hostname: WIN7-20140429JO

#Implementation: synthesis

#Tue May 13 14:14:19 2014

<a name=compilerReport1>$ Start of Compile</a>
#Tue May 13 14:14:19 2014

Synopsys Verilog Compiler, version comp520rcp1, Build 028R, built Sep 23 2010
@N: : <!@TM:1399961664> | Running in 32-bit mode 
Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved

@I::"d:\Microsemi\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.v"
@I::"d:\Microsemi\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\vlog\hypermods.v"
@I::"D:\Actelprj\simdb-fpga\hdl\freq_dop.v"
@I::"D:\Actelprj\simdb-fpga\hdl\freq.v"
@I::"D:\Actelprj\simdb-fpga\hdl\led.v"
@I::"D:\Actelprj\simdb-fpga\hdl\sim_db_fpga.v"
Verilog syntax check successful!
File D:\Actelprj\simdb-fpga\hdl\sim_db_fpga.v changed - recompiling
Selecting top level module sim_db
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="d:\Microsemi\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.v:1168:7:1168:12:@N:CG364:@XP_MSG">proasic3.v(1168)</a><!@TM:1399961664> | Synthesizing module INBUF

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="d:\Microsemi\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.v:1959:7:1959:13:@N:CG364:@XP_MSG">proasic3.v(1959)</a><!@TM:1399961664> | Synthesizing module CLKINT

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="D:\Actelprj\simdb-fpga\hdl\freq_dop.v:18:7:18:15:@N:CG364:@XP_MSG">freq_dop.v(18)</a><!@TM:1399961664> | Synthesizing module freq_dop

@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="D:\Actelprj\simdb-fpga\hdl\freq_dop.v:84:35:84:40:@N:CG179:@XP_MSG">freq_dop.v(84)</a><!@TM:1399961664> | Removing redundant assignment
<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="D:\Actelprj\simdb-fpga\hdl\freq_dop.v:40:0:40:6:@W:CL265:@XP_MSG">freq_dop.v(40)</a><!@TM:1399961664> | Pruning bit 0 of R_I_freq[27:0] - not in use ...</font>

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="D:\Actelprj\simdb-fpga\hdl\freq.v:21:7:21:11:@N:CG364:@XP_MSG">freq.v(21)</a><!@TM:1399961664> | Synthesizing module freq

<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="D:\Actelprj\simdb-fpga\hdl\freq.v:66:3:66:9:@W:CL265:@XP_MSG">freq.v(66)</a><!@TM:1399961664> | Pruning bit 30 of R_I_pha[30:0] - not in use ...</font>

<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="D:\Actelprj\simdb-fpga\hdl\freq.v:66:3:66:9:@W:CL265:@XP_MSG">freq.v(66)</a><!@TM:1399961664> | Pruning bit 29 of R_I_pha[30:0] - not in use ...</font>

<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="D:\Actelprj\simdb-fpga\hdl\freq.v:66:3:66:9:@W:CL265:@XP_MSG">freq.v(66)</a><!@TM:1399961664> | Pruning bit 28 of R_I_pha[30:0] - not in use ...</font>

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="D:\Actelprj\simdb-fpga\hdl\led.v:21:7:21:10:@N:CG364:@XP_MSG">led.v(21)</a><!@TM:1399961664> | Synthesizing module led

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="D:\Actelprj\simdb-fpga\hdl\sim_db_fpga.v:32:7:32:13:@N:CG364:@XP_MSG">sim_db_fpga.v(32)</a><!@TM:1399961664> | Synthesizing module sim_db

<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="D:\Actelprj\simdb-fpga\hdl\sim_db_fpga.v:353:0:353:6:@W:CL169:@XP_MSG">sim_db_fpga.v(353)</a><!@TM:1399961664> | Pruning Register R_I_lcs_n_1 </font>

<font color=#A52A2A>@W:<a href="@W:CL159:@XP_HELP">CL159</a> : <a href="D:\Actelprj\simdb-fpga\hdl\sim_db_fpga.v:41:20:41:26:@W:CL159:@XP_MSG">sim_db_fpga.v(41)</a><!@TM:1399961664> | Input I_lclk is unused</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="D:\Actelprj\simdb-fpga\hdl\led.v:33:4:33:10:@W:CL190:@XP_MSG">led.v(33)</a><!@TM:1399961664> | Optimizing register bit R_cnt[25] to a constant 0</font>
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="D:\Actelprj\simdb-fpga\hdl\led.v:33:4:33:10:@W:CL260:@XP_MSG">led.v(33)</a><!@TM:1399961664> | Pruning Register bit 25 of R_cnt[25:0] </font>

@END
Process took 0h:00m:04s realtime, 0h:00m:04s cputime
# Tue May 13 14:14:24 2014

###########################################################]

</pre></samp></body></html>
<a name=mapperReport2>Synopsys Actel Technology Mapper, Version mapact, Build 023R, Built Sep 29 2010 09:29:00</a>
Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved
Product Version E-2010.09A-1
@N:<a href="@N:MF249:@XP_HELP">MF249</a> : <!@TM:1399961703> | Running in 32-bit mode. 
@N:<a href="@N:MF258:@XP_HELP">MF258</a> : <!@TM:1399961703> | Gated clock conversion disabled  


Available hyper_sources - for debug and ip models
	None Found

Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB)

@N: : <a href="d:\actelprj\simdb-fpga\hdl\freq_dop.v:40:0:40:6:@N::@XP_MSG">freq_dop.v(40)</a><!@TM:1399961703> | Found counter in view:work.freq_dop(verilog) inst R_count[27:0]
@N: : <a href="d:\actelprj\simdb-fpga\hdl\freq.v:66:3:66:9:@N::@XP_MSG">freq.v(66)</a><!@TM:1399961703> | Found counter in view:work.freq(verilog) inst cnt[28:0]
@N:<a href="@N:MF179:@XP_HELP">MF179</a> : <a href="d:\actelprj\simdb-fpga\hdl\freq.v:201:20:201:59:@N:MF179:@XP_MSG">freq.v(201)</a><!@TM:1399961703> | Found 29 bit by 29 bit '<' comparator, 'un1_cnt_31'
@N:<a href="@N:MF179:@XP_HELP">MF179</a> : <a href="d:\actelprj\simdb-fpga\hdl\freq.v:179:31:179:57:@N:MF179:@XP_MSG">freq.v(179)</a><!@TM:1399961703> | Found 27 bit by 27 bit '<' comparator, 'un1_cnt_29'
@N: : <a href="d:\actelprj\simdb-fpga\hdl\freq.v:66:3:66:9:@N::@XP_MSG">freq.v(66)</a><!@TM:1399961703> | Found counter in view:work.freq_0(verilog) inst cnt[28:0]
@N:<a href="@N:MF179:@XP_HELP">MF179</a> : <a href="d:\actelprj\simdb-fpga\hdl\freq.v:201:20:201:59:@N:MF179:@XP_MSG">freq.v(201)</a><!@TM:1399961703> | Found 29 bit by 29 bit '<' comparator, 'un1_cnt_31'
@N:<a href="@N:MF179:@XP_HELP">MF179</a> : <a href="d:\actelprj\simdb-fpga\hdl\freq.v:179:31:179:57:@N:MF179:@XP_MSG">freq.v(179)</a><!@TM:1399961703> | Found 27 bit by 27 bit '<' comparator, 'un1_cnt_29'
@N:<a href="@N:MF238:@XP_HELP">MF238</a> : <a href="d:\actelprj\simdb-fpga\hdl\led.v:47:21:47:34:@N:MF238:@XP_MSG">led.v(47)</a><!@TM:1399961703> | Found 25 bit incrementor, 'un3_R_cnt_1[24:0]'
Finished factoring (Time elapsed 0h:00m:11s; Memory used current: 66MB peak: 67MB)

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:12s; Memory used current: 73MB peak: 73MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:16s; Memory used current: 80MB peak: 82MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:17s; Memory used current: 81MB peak: 82MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:18s; Memory used current: 81MB peak: 82MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:19s; Memory used current: 80MB peak: 82MB)

Finished preparing to map (Time elapsed 0h:00m:21s; Memory used current: 81MB peak: 82MB)


High Fanout Net Report
**********************

Driver Instance / Pin Name                    Fanout, notes                     
--------------------------------------------------------------------------------
R_OUTPUT_CONTROL[12] / Q                      37                                
module_freq6.R_pluse_number_0_sqmuxa / Y      48                                
module_freq5.R_pluse_number_0_sqmuxa / Y      48                                
module_freq4.R_pluse_number_0_sqmuxa / Y      48                                
module_freq3.R_pluse_number_0_sqmuxa / Y      48                                
module_freq2.R_pluse_number_0_sqmuxa / Y      48                                
module_freq1.R_pluse_number_0_sqmuxa / Y      48                                
IO_ld_pad[0] / Y                              50                                
IO_ld_pad[1] / Y                              50                                
IO_ld_pad[2] / Y                              48                                
IO_ld_pad[3] / Y                              47                                
IO_ld_pad[4] / Y                              47                                
IO_ld_pad[5] / Y                              47                                
IO_ld_pad[6] / Y                              46                                
IO_ld_pad[7] / Y                              46                                
IO_ld_pad[8] / Y                              46                                
IO_ld_pad[9] / Y                              46                                
IO_ld_pad[10] / Y                             46                                
IO_ld_pad[11] / Y                             46                                
IO_ld_pad[12] / Y                             46                                
IO_ld_pad[13] / Y                             44                                
IO_ld_pad[14] / Y                             44                                
IO_ld_pad[15] / Y                             44                                
I_la_pad[1] / Y                               375                               
I_la_pad[2] / Y                               155                               
I_la_pad[3] / Y                               124                               
I_la_pad[4] / Y                               57                                
I_la_pad[5] / Y                               101                               
I_la_pad[6] / Y                               38                                
i_CLKINT2 / Y                                 1753 : 1746 asynchronous set/reset
module_freq2.cnt_0_sqmuxa / Y                 30                                
un1_R_OUTPUT_CONTROL / Y                      55                                
module_freq4.R_I_freq_0_sqmuxa_1 / Y          58                                
un1_R_OUTPUT_CONTROL_4_i_a2 / Y               55                                
module_freq5.cnt_0_sqmuxa / Y                 30                                
module_freq1.cnt_0_sqmuxa / Y                 30                                
module_freq1.R_I_freq_0_sqmuxa_1 / Y          58                                
un1_R_OUTPUT_CONTROL_2 / Y                    54                                
module_freq3.R_I_freq_0_sqmuxa_1 / Y          58                                
module_freq3.cnt_0_sqmuxa / Y                 30                                
module_freq4.cnt_0_sqmuxa / Y                 30                                
un1_R_OUTPUT_CONTROL_3_i_a2 / Y               55                                
module_freq6.R_I_freq_0_sqmuxa_1 / Y          58                                
module_freq6.cnt_0_sqmuxa / Y                 30                                
un1_R_OUTPUT_CONTROL_5_i_a2 / Y               55                                
module_freq_dop.R_I_freq_1_sqmuxa_i / Y       27                                
module_freq_dop.R_count_0_sqmuxa_i_o2 / Y     28                                
module_freq5.R_I_freq_0_sqmuxa_1 / Y          58                                
un1_R_OUTPUT_CONTROL_1 / Y                    55                                
module_freq2.R_I_freq_0_sqmuxa_1 / Y          58                                
module_freq5.un1_R_spd123_1 / Y               33                                
module_freq6.un1_R_spd123_1 / Y               33                                
module_freq6.R_pulse_cnt_8_sn_m1_0_a2 / Y     32                                
module_freq5.R_pulse_cnt_8_sn_m1_0_a2 / Y     32                                
module_freq4.R_pulse_cnt_8_sn_m1_0_a2 / Y     32                                
module_freq3.R_pulse_cnt_8_sn_m1_0_a2 / Y     32                                
module_freq2.R_pulse_cnt_8_sn_m1_0_a2 / Y     32                                
module_freq1.R_pulse_cnt_8_sn_m1_0_a2 / Y     32                                
================================================================================

@N:<a href="@N:FP130:@XP_HELP">FP130</a> : <!@TM:1399961703> | Promoting Net I_la_c[1] on CLKINT  I_1037  
@N:<a href="@N:FP130:@XP_HELP">FP130</a> : <!@TM:1399961703> | Promoting Net I_la_c[2] on CLKINT  I_1038  
@N:<a href="@N:FP130:@XP_HELP">FP130</a> : <!@TM:1399961703> | Promoting Net I_la_c[3] on CLKINT  I_1039  
@N:<a href="@N:FP130:@XP_HELP">FP130</a> : <!@TM:1399961703> | Promoting Net I_la_c[5] on CLKINT  I_1040  
Replicating Combinational Instance module_freq1.R_pulse_cnt_8_sn_m1_0_a2, fanout 32 segments 2
Replicating Combinational Instance module_freq2.R_pulse_cnt_8_sn_m1_0_a2, fanout 32 segments 2
Replicating Combinational Instance module_freq3.R_pulse_cnt_8_sn_m1_0_a2, fanout 32 segments 2
Replicating Combinational Instance module_freq4.R_pulse_cnt_8_sn_m1_0_a2, fanout 32 segments 2
Replicating Combinational Instance module_freq5.R_pulse_cnt_8_sn_m1_0_a2, fanout 32 segments 2
Replicating Combinational Instance module_freq6.R_pulse_cnt_8_sn_m1_0_a2, fanout 32 segments 2
Replicating Combinational Instance module_freq6.un1_R_spd123_1, fanout 33 segments 2
Replicating Combinational Instance module_freq5.un1_R_spd123_1, fanout 33 segments 2
Replicating Combinational Instance module_freq2.R_I_freq_0_sqmuxa_1, fanout 58 segments 3
Replicating Combinational Instance un1_R_OUTPUT_CONTROL_1, fanout 57 segments 3
Replicating Combinational Instance module_freq5.R_I_freq_0_sqmuxa_1, fanout 58 segments 3
Replicating Combinational Instance module_freq_dop.R_count_0_sqmuxa_i_o2, fanout 28 segments 2
Replicating Combinational Instance module_freq_dop.R_I_freq_1_sqmuxa_i, fanout 27 segments 2
Replicating Combinational Instance un1_R_OUTPUT_CONTROL_5_i_a2, fanout 55 segments 3
Replicating Combinational Instance module_freq6.cnt_0_sqmuxa, fanout 30 segments 2
Replicating Combinational Instance module_freq6.R_I_freq_0_sqmuxa_1, fanout 58 segments 3
Replicating Combinational Instance un1_R_OUTPUT_CONTROL_3_i_a2, fanout 55 segments 3
Replicating Combinational Instance module_freq4.cnt_0_sqmuxa, fanout 30 segments 2
Replicating Combinational Instance module_freq3.cnt_0_sqmuxa, fanout 30 segments 2
Replicating Combinational Instance module_freq3.R_I_freq_0_sqmuxa_1, fanout 58 segments 3
Replicating Combinational Instance un1_R_OUTPUT_CONTROL_2, fanout 56 segments 3
Replicating Combinational Instance module_freq1.R_I_freq_0_sqmuxa_1, fanout 58 segments 3
Replicating Combinational Instance module_freq1.cnt_0_sqmuxa, fanout 30 segments 2
Replicating Combinational Instance module_freq5.cnt_0_sqmuxa, fanout 30 segments 2
Replicating Combinational Instance un1_R_OUTPUT_CONTROL_4_i_a2, fanout 57 segments 3
Replicating Combinational Instance module_freq4.R_I_freq_0_sqmuxa_1, fanout 58 segments 3
Replicating Combinational Instance un1_R_OUTPUT_CONTROL, fanout 57 segments 3
Replicating Combinational Instance module_freq2.cnt_0_sqmuxa, fanout 30 segments 2
Buffering I_la_c[6], fanout 38 segments 2
Buffering I_la_c[4], fanout 57 segments 3
Replicating Combinational Instance module_freq1.R_pluse_number_0_sqmuxa, fanout 48 segments 2
Replicating Combinational Instance module_freq2.R_pluse_number_0_sqmuxa, fanout 48 segments 2
Replicating Combinational Instance module_freq3.R_pluse_number_0_sqmuxa, fanout 48 segments 2
Replicating Combinational Instance module_freq4.R_pluse_number_0_sqmuxa, fanout 48 segments 2
Replicating Combinational Instance module_freq5.R_pluse_number_0_sqmuxa, fanout 48 segments 2
Replicating Combinational Instance module_freq6.R_pluse_number_0_sqmuxa, fanout 48 segments 2
Replicating Sequential Instance R_OUTPUT_CONTROL[12], fanout 39 segments 2
Finished technology mapping (Time elapsed 0h:00m:23s; Memory used current: 79MB peak: 82MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:24s; Memory used current: 79MB peak: 82MB)


Added 3 Buffers
Added 47 Cells via replication
	Added 1 Sequential Cells via replication
	Added 46 Combinational Cells via replication
Finished restoring hierarchy (Time elapsed 0h:00m:25s; Memory used current: 79MB peak: 82MB)

Writing Analyst data base D:\Actelprj\simdb-fpga\synthesis\SIM_DB.srm
Finished Writing Netlist Databases (Time elapsed 0h:00m:28s; Memory used current: 75MB peak: 82MB)

Writing EDIF Netlist and constraint files
E-2010.09A-1
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:30s; Memory used current: 77MB peak: 82MB)

<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1399961703> | Found inferred clock sim_db|clock with period 40.00ns. A user-defined clock should be declared on object "p:clock"</font> 



<a name=timingReport3>##### START OF TIMING REPORT #####[</a>
# Timing Report written on Tue May 13 14:15:02 2014
#


Top view:               sim_db
Library name:           PA3
Operating conditions:   COMWC-2 ( T = 70.0, V = 1.42, P = 1.30, tree_type = balanced_tree )
Requested Frequency:    25.0 MHz
Wire load mode:         top
Wire load model:        proasic3
Paths requested:        5
Constraint File(s):    
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1399961703> | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. 

@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1399961703> | Clock constraints cover only FF-to-FF paths associated with the clock.. 



<a name=performanceSummary4>Performance Summary </a>
*******************


Worst slack in design: 19.518

                   Requested     Estimated     Requested     Estimated                Clock        Clock              
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group              
----------------------------------------------------------------------------------------------------------------------
sim_db|clock       25.0 MHz      48.8 MHz      40.000        20.482        19.518     inferred     Inferred_clkgroup_0
======================================================================================================================





<a name=clockRelationships5>Clock Relationships</a>
*******************

Clocks                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-------------------------------------------------------------------------------------------------------------------
Starting      Ending        |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-------------------------------------------------------------------------------------------------------------------
sim_db|clock  sim_db|clock  |  40.000      19.518  |  No paths    -      |  No paths    -      |  No paths    -    
===================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



<a name=interfaceInfo6>Interface Information </a>
*********************

		No IO constraint found 



====================================
<a name=clockReport7>Detailed Report for Clock: sim_db|clock</a>
====================================



<a name=startingSlack8>Starting Points with Worst Slack</a>
********************************

                               Starting                                           Arrival           
Instance                       Reference        Type       Pin     Net            Time        Slack 
                               Clock                                                                
----------------------------------------------------------------------------------------------------
module_freq_dop.R_count[0]     sim_db|clock     DFN1C0     Q       R_count[0]     0.434       19.518
module_freq_dop.R_count[1]     sim_db|clock     DFN1C0     Q       R_count[1]     0.434       19.610
module_freq2.cnt[25]           sim_db|clock     DFN1C0     Q       cnt[25]        0.550       19.878
module_freq1.cnt[15]           sim_db|clock     DFN1C0     Q       cnt[15]        0.550       19.920
module_freq1.cnt[0]            sim_db|clock     DFN1C0     Q       cnt[0]         0.550       19.921
module_freq5.cnt[25]           sim_db|clock     DFN1C0     Q       cnt[25]        0.550       19.982
module_freq2.cnt[15]           sim_db|clock     DFN1C0     Q       cnt[15]        0.550       19.983
module_freq1.cnt[16]           sim_db|clock     DFN1C0     Q       cnt[16]        0.550       20.008
module_freq5.cnt[15]           sim_db|clock     DFN1C0     Q       cnt[15]        0.550       20.087
module_freq1.cnt[2]            sim_db|clock     DFN1C0     Q       cnt[2]         0.550       20.088
====================================================================================================


<a name=endingSlack9>Ending Points with Worst Slack</a>
******************************

                                 Starting                                                  Required           
Instance                         Reference        Type       Pin     Net                   Time         Slack 
                                 Clock                                                                        
--------------------------------------------------------------------------------------------------------------
module_freq_dop.R_count[27]      sim_db|clock     DFN1C0     D       N_31                  39.598       19.518
module_freq2.R_pulse_cnt[31]     sim_db|clock     DFN1C0     D       R_pulse_cnt_8[31]     39.598       19.878
module_freq1.R_pulse_cnt[31]     sim_db|clock     DFN1C0     D       R_pulse_cnt_8[31]     39.598       19.920
module_freq5.R_pulse_cnt[31]     sim_db|clock     DFN1C0     D       R_pulse_cnt_8[31]     39.598       19.982
module_freq6.R_pulse_cnt[31]     sim_db|clock     DFN1C0     D       R_pulse_cnt_8[31]     39.598       20.120
module_freq4.R_pulse_cnt[31]     sim_db|clock     DFN1C0     D       R_pulse_cnt_8[31]     39.598       20.120
module_freq_dop.R_count[26]      sim_db|clock     DFN1C0     D       N_29                  39.598       20.143
module_freq_dop.R_count[25]      sim_db|clock     DFN1C0     D       R_count_n25           39.598       20.392
module_freq2.R_pulse_cnt[30]     sim_db|clock     DFN1C0     D       R_pulse_cnt_8[30]     39.598       20.483
module_freq2.R_pulse_cnt[29]     sim_db|clock     DFN1C0     D       R_pulse_cnt_8[29]     39.598       20.531
==============================================================================================================



<a name=worstPaths10>Worst Path Information</a>
<a href="D:\Actelprj\simdb-fpga\synthesis\SIM_DB.srr:fp:21111:29454:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      40.000
    - Setup time:                            0.402
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         39.598

    - Propagation time:                      20.080
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     19.518

    Number of logic level(s):                26
    Starting point:                          module_freq_dop.R_count[0] / Q
    Ending point:                            module_freq_dop.R_count[27] / D
    The start point is clocked by            sim_db|clock [rising] on pin CLK
    The end   point is clocked by            sim_db|clock [rising] on pin CLK

Instance / Net                                      Pin      Pin               Arrival     No. of    
Name                                     Type       Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------
module_freq_dop.R_count[0]               DFN1C0     Q        Out     0.434     0.434       -         
R_count[0]                               Net        -        -       0.955     -           5         
module_freq_dop.R_count_RNI7QN[1]        OR2B       B        In      -         1.389       -         
module_freq_dop.R_count_RNI7QN[1]        OR2B       Y        Out     0.386     1.774       -         
N_58                                     Net        -        -       0.288     -           2         
module_freq_dop.R_count_RNICT31[2]       OR2A       B        In      -         2.063       -         
module_freq_dop.R_count_RNICT31[2]       OR2A       Y        Out     0.483     2.545       -         
N_59                                     Net        -        -       0.288     -           2         
module_freq_dop.R_count_RNII4G1[3]       OR2A       B        In      -         2.833       -         
module_freq_dop.R_count_RNII4G1[3]       OR2A       Y        Out     0.483     3.316       -         
N_60                                     Net        -        -       0.288     -           2         
module_freq_dop.R_count_RNIPFS1[4]       OR2A       B        In      -         3.604       -         
module_freq_dop.R_count_RNIPFS1[4]       OR2A       Y        Out     0.483     4.087       -         
N_61                                     Net        -        -       0.602     -           3         
module_freq_dop.R_count_RNIAIL2[6]       NOR3B      C        In      -         4.690       -         
module_freq_dop.R_count_RNIAIL2[6]       NOR3B      Y        Out     0.365     5.054       -         
N_37                                     Net        -        -       0.288     -           2         
module_freq_dop.R_count_RNIK923[7]       NOR2B      B        In      -         5.343       -         
module_freq_dop.R_count_RNIK923[7]       NOR2B      Y        Out     0.386     5.728       -         
N_39                                     Net        -        -       0.288     -           2         
module_freq_dop.R_count_RNIV4F3[8]       NOR2B      B        In      -         6.016       -         
module_freq_dop.R_count_RNIV4F3[8]       NOR2B      Y        Out     0.386     6.402       -         
N_42                                     Net        -        -       0.288     -           2         
module_freq_dop.R_count_RNIB4S3[9]       NOR2B      B        In      -         6.690       -         
module_freq_dop.R_count_RNIB4S3[9]       NOR2B      Y        Out     0.386     7.075       -         
N_46                                     Net        -        -       0.288     -           2         
module_freq_dop.R_count_RNIVQT7[10]      OR2B       B        In      -         7.364       -         
module_freq_dop.R_count_RNIVQT7[10]      OR2B       Y        Out     0.386     7.749       -         
N_67                                     Net        -        -       0.288     -           2         
module_freq_dop.R_count_RNIKHVB[11]      OR2A       B        In      -         8.037       -         
module_freq_dop.R_count_RNIKHVB[11]      OR2A       Y        Out     0.483     8.520       -         
N_68                                     Net        -        -       0.288     -           2         
module_freq_dop.R_count_RNIA81G[12]      OR2A       B        In      -         8.808       -         
module_freq_dop.R_count_RNIA81G[12]      OR2A       Y        Out     0.483     9.291       -         
N_69                                     Net        -        -       0.288     -           2         
module_freq_dop.R_count_RNI1V2K[13]      OR2A       B        In      -         9.579       -         
module_freq_dop.R_count_RNI1V2K[13]      OR2A       Y        Out     0.483     10.062      -         
N_70                                     Net        -        -       0.288     -           2         
module_freq_dop.R_count_RNIPL4O[14]      OR2A       B        In      -         10.350      -         
module_freq_dop.R_count_RNIPL4O[14]      OR2A       Y        Out     0.483     10.833      -         
N_71                                     Net        -        -       0.288     -           2         
module_freq_dop.R_count_RNIIC6S[15]      OR2A       B        In      -         11.121      -         
module_freq_dop.R_count_RNIIC6S[15]      OR2A       Y        Out     0.483     11.604      -         
N_72                                     Net        -        -       0.288     -           2         
module_freq_dop.R_count_RNIC3801[16]     OR2A       B        In      -         11.892      -         
module_freq_dop.R_count_RNIC3801[16]     OR2A       Y        Out     0.483     12.375      -         
N_73                                     Net        -        -       0.288     -           2         
module_freq_dop.R_count_RNI7Q941[17]     NOR2A      B        In      -         12.663      -         
module_freq_dop.R_count_RNI7Q941[17]     NOR2A      Y        Out     0.304     12.967      -         
N_74                                     Net        -        -       0.288     -           2         
module_freq_dop.R_count_RNI3HB81[18]     NOR2B      B        In      -         13.255      -         
module_freq_dop.R_count_RNI3HB81[18]     NOR2B      Y        Out     0.386     13.641      -         
N_38                                     Net        -        -       0.288     -           2         
module_freq_dop.R_count_RNI08DC1[19]     NOR2B      B        In      -         13.929      -         
module_freq_dop.R_count_RNI08DC1[19]     NOR2B      Y        Out     0.386     14.314      -         
N_41                                     Net        -        -       0.288     -           2         
module_freq_dop.R_count_RNIN2FG1[20]     NOR2B      B        In      -         14.603      -         
module_freq_dop.R_count_RNIN2FG1[20]     NOR2B      Y        Out     0.386     14.988      -         
N_45                                     Net        -        -       0.288     -           2         
module_freq_dop.R_count_RNIFTGK1[21]     OR2B       B        In      -         15.276      -         
module_freq_dop.R_count_RNIFTGK1[21]     OR2B       Y        Out     0.386     15.662      -         
N_78                                     Net        -        -       0.288     -           2         
module_freq_dop.R_count_RNI8OIO1[22]     OR2A       B        In      -         15.950      -         
module_freq_dop.R_count_RNI8OIO1[22]     OR2A       Y        Out     0.483     16.433      -         
N_79                                     Net        -        -       0.288     -           2         
module_freq_dop.R_count_RNI2JKS1[23]     OR2A       B        In      -         16.721      -         
module_freq_dop.R_count_RNI2JKS1[23]     OR2A       Y        Out     0.483     17.204      -         
N_80                                     Net        -        -       0.288     -           2         
module_freq_dop.R_count_RNITDM02[24]     OR2A       B        In      -         17.492      -         
module_freq_dop.R_count_RNITDM02[24]     OR2A       Y        Out     0.483     17.975      -         
N_81                                     Net        -        -       0.288     -           2         
module_freq_dop.R_count_RNIP8O42[25]     NOR2A      B        In      -         18.263      -         
module_freq_dop.R_count_RNIP8O42[25]     NOR2A      Y        Out     0.304     18.567      -         
N_43                                     Net        -        -       0.288     -           2         
module_freq_dop.R_count_RNO_0[27]        NOR2B      B        In      -         18.855      -         
module_freq_dop.R_count_RNO_0[27]        NOR2B      Y        Out     0.386     19.240      -         
N_44                                     Net        -        -       0.240     -           1         
module_freq_dop.R_count_RNO[27]          XA1        A        In      -         19.480      -         
module_freq_dop.R_count_RNO[27]          XA1        Y        Out     0.359     19.840      -         
N_31                                     Net        -        -       0.240     -           1         
module_freq_dop.R_count[27]              DFN1C0     D        In      -         20.080      -         
=====================================================================================================
Total path delay (propagation time + setup) of 20.482 is 11.816(57.7%) logic and 8.666(42.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Target Part: A3P400_FBGA256_-2
<a name=cellreport11>Report for cell sim_db.verilog</a>
  Core Cell usage:
              cell count     area count*area
              AND2   374      1.0      374.0
             AND2A    72      1.0       72.0
              AND3   166      1.0      166.0
             AND3A     6      1.0        6.0
               AO1   232      1.0      232.0
              AO1A     6      1.0        6.0
              AO1B     5      1.0        5.0
              AO1C    92      1.0       92.0
              AO1D     2      1.0        2.0
              AOI1    21      1.0       21.0
             AOI1A   126      1.0      126.0
             AOI1B    28      1.0       28.0
               AX1    18      1.0       18.0
              AX1A     7      1.0        7.0
              AX1C     7      1.0        7.0
              AX1E    12      1.0       12.0
              BUFF     3      1.0        3.0
            CLKINT     6      0.0        0.0
               GND     9      0.0        0.0
               INV     7      1.0        7.0
               MX2   762      1.0      762.0
              MX2A     1      1.0        1.0
              MX2C   292      1.0      292.0
              NOR2   575      1.0      575.0
             NOR2A   344      1.0      344.0
             NOR2B   317      1.0      317.0
              NOR3    15      1.0       15.0
             NOR3A   169      1.0      169.0
             NOR3B    51      1.0       51.0
             NOR3C   281      1.0      281.0
               OA1    36      1.0       36.0
              OA1A    54      1.0       54.0
              OA1C     8      1.0        8.0
              OAI1    40      1.0       40.0
               OR2    20      1.0       20.0
              OR2A   294      1.0      294.0
              OR2B   150      1.0      150.0
              OR3A     9      1.0        9.0
              OR3B    27      1.0       27.0
              OR3C    28      1.0       28.0
               VCC     9      0.0        0.0
               XA1    11      1.0       11.0
              XA1A   139      1.0      139.0
              XA1B    48      1.0       48.0
              XA1C    55      1.0       55.0
             XNOR2   635      1.0      635.0
              XOR2   528      1.0      528.0


              DFN1     6      1.0        6.0
            DFN1C0   491      1.0      491.0
          DFN1E0C0    24      1.0       24.0
          DFN1E0P0    96      1.0       96.0
          DFN1E1C0  1134      1.0     1134.0
            DFN1P0     2      1.0        2.0
                   -----          ----------
             TOTAL  7850              7826.0


  IO Cell usage:
              cell count
             BIBUF    16
             INBUF    19
            OUTBUF    58
                   -----
             TOTAL    93


Core Cells         : 7826 of 9216 (85%)
IO Cells           : 93

  RAM/ROM Usage Summary
Block Rams : 0 of 12 (0%)

Mapper successful!
Process took 0h:00m:37s realtime, 0h:00m:31s cputime
# Tue May 13 14:15:02 2014

###########################################################]

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